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1nm hegemony "secret war" begins

2022-02-02 12:49:00 TechWeb

Semiconductor industry observation (ID:icbank)| source

Chang Qiu | author

No secondary reprint is provided

The semiconductor process has progressed to 3nm, Trial production began this year , Mass production will be realized next year , After that, we will go to 2nm and 1nm Go ahead . be relative to 2nm, current 1nm The process technology is completely in the stage of R & D and exploration , There is no landing technology and capacity planning , That's why , bring 1nm Technology has more room for imagination and expansion , Industry, University and research circles all over the world are conducting research on relevant processes and materials .

Last week, ,IBM And Samsung unveiled a new design for vertically stacking transistors on a chip , It is called vertical transmission field effect transistor (Vertical Transport Field Effect Transistors,VTFET). Current processors and SoC, The crystal tube is placed flat on the silicon surface , Then the current flows from one side to the other . by comparison ,VTFET Perpendicular to each other , The current flows vertically . This technology is expected to break through 1nm Process bottlenecks .

IBM And Samsung said , This design has two advantages . First , It can bypass many performance limitations , Extend Moore's law to IBM Beyond the current nano chip technology , what's more , Due to the greater current , The design reduces energy waste , They estimated that VTFET Will make the processor faster than using FinFET Transistor designed chips are twice as fast or reduce power consumption 85%.IBM And Samsung claim , This technology is expected to allow mobile phones to be used for a whole week on a single charge . They said , It can also make certain energy intensive tasks ( Including infill mining ) More energy saving , Therefore, it has little impact on the environment .

IBM And Samsung have not revealed when they plan to commercialize the process technology . They are not the only one trying to break through 1 nm Bottleneck companies . This year, 5 month , TSMC and its partners released 1nm Process technology path ;7 month , Intel Express , The goal is to 2024 Completed the design of Egyptian chip before . The company plans to use its new “ Intel 20A” Process nodes and RibbonFET Transistors to achieve this goal .

01、 TSMC remains the pioneer

In recent years , The scientific community has been looking for two-dimensional materials that can replace silicon , Challenge 1nm The following manufacturing processes , However, the high resistance of two-dimensional materials has not been solved so far 、 Low current problem .

In recent years, , In the development and commercialization of advanced processes , TSMC has always been a pioneer in the industry .

This year, 5 month , TSMC 、 National Taiwan University China (NTU) And MIT (MIT) Joint announcement ,1nm Major breakthroughs have been made in chip research and development .

The breakthrough is mainly reflected in materials , Use semi metallic bismuth (Bi) As a two-dimensional (2D) Contact electrode of material , It can greatly reduce the resistance and increase the current . This can achieve energy efficiency close to the physical limits of the existing semiconductor size . The message is in IBM Earlier announced its 2nm Released after the chip .

Every new process technology will bring new challenges , under these circumstances , The key challenge is to find the right transistor structure and material . meanwhile , Transistor contacts that supply power to transistors are critical to their performance . The further miniaturization of semiconductor technology increases the contact resistance , This limits their performance . therefore , Chip manufacturers need to find a very low resistance 、 Contact material that can transmit large current and can be used for mass production .

Using semi metallic bismuth as the contact electrode of the transistor can greatly reduce the resistance and increase the current . at present , TSMC uses tungsten interconnection transistors , Intel uses cobalt interconnect . Both have their advantages , And they all need specific equipment and tools .

In order to use semi metallic bismuth as the contact electrode of the transistor , Researchers had to use a helium ion beam (HIB) Lithography system and design a “ Simple deposition process ”. This process is only used to develop production lines , Therefore, it is not fully ready for mass production .

at present , TSMC 1nm The process node is still in the exploratory stage , The factory is trying various options , There is no guarantee that semi metallic bismuth will be used in mass production in the future .

02、IMEC Point to 2027

In recent days, , Belgium Microelectronics Research Center (IMEC) Express ,1nm Process 2027 Commercialization can be achieved in , After that 0.7nm Is expected to be in 2029 Mass production will be realized in two years .

IMEC Of CEO Luc Van den hove In an interview, the doctor stressed , With new technology ,“ It's not a problem how many generations Moore's law has to go forward .” It is reported that ,IMEC and ASML Cooperative EUV Equipment research and development is in progress , Japan's TEL And get involved , It is expected that the test equipment is expected to 2023 Completed at the beginning of the year , There are also enterprises planning to 2026 Annual mass production .

Besides ,IMEC A new method has also been developed , Can be used in 1nm Metal interconnects are used in chips constructed by process technology to reduce Joule heat effect .

IMEC The researchers say , In the experimental study of binary compounds based on aluminum , Focus on its resistivity , Stoichiometric AlCu and Al2Cu The resistivity of the film is as low as 9.5µΩcm. These results experimentally support their promise as new conductors in advanced semi mosaic interconnect integration schemes , In these programs , They can be combined with the air gap to improve performance . However , In this combination , Joule heating effect is becoming more and more important . This is through 12 Layer back end (BEOL) The structure is predicted by combining experimental and modeling work .

1nm The process requires the introduction of new conductor materials in the most critical layer at the back end , Such as binary and ternary intermetallic compounds ( for example ,Al or Ru The base ), Its resistivity is lower than that of conventional elemental metals of proportional size ( for example Cu、Co、Mo or Ru).IMEC The resistivity of aluminide films has been studied experimentally , Include AlNi、Al 3 Sc、AlCu and Al 2 Cu. stay 20nm And above , all PVD Resistivity and of deposited film Ru or Mo Equivalent or lower .28nm Of AlCu and Al 2 The minimum resistivity of the film reaches 9.5 µΩcmCu – lower than Cu Value .

IMEC It is envisaged to introduce intermetallic compounds into advanced semi mosaic integration schemes , Includes lines that directly etch patternable metal to achieve a higher aspect ratio . By gradually introducing part or all of the air gap between the metal wires , Can be further improved RC Delay . Replace the traditional low-voltage with electrically isolated air gap k Dielectrics are expected to reduce proportionally sized capacitance . But the thermal conductivity of the air gap is very poor , This raises concerns about Joule heat under operating conditions .

IMEC Through local 2 The layer metal interconnect level performs Joule heating “ calibration ” Measure and project the results to 12 layer BEOL structure , Quantifying this challenge . The study predicts , The air gap will raise the temperature 20%. It is found that the density of metal wires plays an important role : Higher metal density shows that it helps to reduce Joule heat .

“ These research results are to improve the semi inlaid metallization scheme as 1nm The key to process interconnection options ,” IMEC Researcher and director of nano interconnection project Zsolt Tokei say .“ Besides ,IMEC Expanding the interconnect roadmap with other options , Including mixed metallization and new intermediate line scheme , While addressing key challenges related to process integration and reliability .”

03、1nm How will it develop later ?

When silicon-based chips break through 1nm after , Quantum tunneling effect increases greatly , Will form “ Electronic runaway ”, Disable the chip . In this case , Replace the silicon substrate of the chip , It may be one of the feasible ways for the further development of chips .

Electrons can flow continuously from one door to the next , Instead of staying in the expected logic gate , This essentially makes it impossible for the transistor to be turned off .

Because the transistor consists of three terminals : Source pole , Drain and grid . The current flows from the source to the drain , And controlled by the grid , The grid turns on or off the current according to the applied voltage .

Silicon and molybdenum disulfide (MoS2) All have lattice structure , But the electron effective mass passing through silicon is smaller than that of molybdenum disulfide . When the gate length is 5nm Or longer , Silicon transistors work properly .

The electrons passing through molybdenum disulfide have higher effective mass , Their flow can be controlled by a smaller door length . Lawrence Berkeley National Laboratory has experimentally verified the feasibility of this scheme , But the study is still at a very early stage .

One 14nm There are more than on the process chip 10 100 million transistors , The Berkeley Lab team has not yet developed a viable way to mass produce new products 1nm The transistor , No chips have even been developed that use such transistors .

But even as proof of concept , The results here are still very important and encouraging , It is expected that the subsequent discovery of new materials can continue to allow smaller transistor sizes , And then improve the energy efficiency of future chips .

04、 China also has bright spots

at present , The global 1nm The manufacturing process is in the stage of R & D and exploration , It will be several years before commercial production . therefore , Although the advanced technology in Chinese mainland is not commercialized. , However, it is also following the international forefront in relevant theoretical research . for example , Hunan University is in 1nm The research of process technology also has a bright performance .

This year, 6 month , The research team of Hunan University has developed an ultra short channel vertical field effect transistor (VFET). This transistor technology , You can do it with transistors 3nm size , The channel length only needs 0.65nm. In previous manufacturing processes , The channel length represents the chip manufacturing process , in other words 0.65nm The length of the channel , Means 0.65nm Process .

That is, the transistors are not arranged in parallel , It's arranged vertically . This longitudinal structure has natural short channel characteristics , The semiconductor channel is located between the bottom electrode and the top electrode , The length of the trench depends only on the thickness of the material .

what's more , This vertical field effect transistor is not arranged in parallel , It's arranged vertically . This longitudinal structure has natural short channel characteristics , The semiconductor channel is located between the bottom electrode and the top electrode , The length of the trench depends only on the thickness of the material .

1

The researchers used van der Waals (vdW) Metal electrode integration method , With molybdenum disulfide (MoS2) As a thin layer or even monatomic layer of semiconductor channel , That is, the channel length , In fact, it is the thickness of a layer of molybdenum disulfide material , So the shortest time is reached 0.65nm. Due to the different arrangement , There is no need to shorten the distance between transistors , It's OK to build a layer of building blocks and go up the base layer by layer , This makes it not completely dependent on high-precision lithography . however , The research is just a product of the laboratory , We should really move towards mass production , There is still a long way to go .

05、 towards 1nm The lithography machine is moving forward

The above is about the research and development of process technology and materials , To achieve 1nm The landing of the process , Manufacturing equipment , especially EUV Lithography machine is essential , It has to be mentioned ASML.

at present ,ASML The main shipment of EUV The lithography machines are NXE:3400B and 3400C, The numerical aperture of these two models (NA) Are all 0.33, One of them is updated 3400C The availability of has been reached 90% about .

ASML expect , By the end of this year ,NXE:3600D Delivery will begin , The matching accuracy of the device is improved , stay 30mJ/cm2 The throughput of wafers under the condition of 160 slice , comparison 3400C Improved 18%, Will become the future of TSMC and Samsung 3nm Main equipment of manufacturing process .

besides ,ASML It also announced the R & D plan of the next three generations of lithography machines , The models of the three models are NEXT、EXE:5000 and EXE:5200. from EXE:5000 Start , The numerical aperture is increased to 0.55.

0.55NA Than 0.33NA Has a huge improvement , Including higher contrast , Lower image exposure costs , It's the future trend .

at present , Silicon 、 The exposure clean room is approaching the physical limit , current 5nm/7nm The lithography machine has become very precise , Equipment parts up to 10 ten thousand +、 The volume is 40 A container . It is reported that ,1nm The lithography machine is larger than it is now 3nm Twice as much .

Because the lithography machine has a lot of parts , High precision assembly is required , Lead to the lithography machine from delivery to configuration / The whole process of training takes up to two years . Calculated according to this reference , expect 0.55NA The large-scale application of 2025~2026 Years. , At that time , The approximate rate is 1nm Trial production period of process technology .

06、 Conclusion

The above is only carried out in the current industry 1nm Representative of process related R & D work , Not all of them . Believe with 3nm Mass production of , as well as 2nm Enter the stage of commercialization ,1nm The research and development of the manufacturing process will gradually mature , These current laboratory level studies , It is estimated that many will land in the wafer factory , meanwhile , There will also be the birth of newer processes and materials technology .

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