current position:Home>Codasip joins hands with Siemens to create the most complete formal verification in risc-v field

Codasip joins hands with Siemens to create the most complete formal verification in risc-v field

2022-05-07 14:53:22TechWeb

【TechWeb】5 month 7 Daily news , A leading enterprise in the field of processor design automation Codasip announce : By adopting Siemens Group Siemens EDA Of OneSpin IC Verification tool , Expand the range of tools available for its formal verification solution , For comprehensive and thorough processor testing .Codasip Continue to invest heavily in processor verification , With persistent efforts to provide the industry with the highest quality RISC-V Processor semiconductor intellectual property (IP).

Siemens EDA Of OneSpin The tool provides an advanced and extremely powerful verification platform , To solve the key chip integrity problem .OneSpin It is an extremely advanced formal verification tool , Suitable for automotive and other high integrity processor applications , Be able to verify the design and implementation with minimal setup and running time .

Thanks to its high quality RISC-V processor ,Codasip Stand out from the competition . at present , There has been a 20 Million star Codasip processor IP The kernel is in use , Most of them are for first-class customers , therefore Codasip We must continue to consistently provide the highest quality processors IP.

Siemens EDA Strategic director of chip design verification department Neil Hand Express :“ We are very happy with Codasip cooperation , Help ensure its RISC-V processor IP The high quality of , And establish optimized solutions for our common customers . our OneSpin Formal verification tools have world-class technology , Include OneSpin RISC-V Validate solution , When they are with Codasip Innovative RISC-V IP Combination , It has formed a key force to help chip designers quickly bring high-quality products to the market .”

Codasip Chief marketing officer of Rupert Baines commented :“ To be frank , some RISC-V IP The poor state of verification is shocking . Developers are right RISC-V IP Quality concerns are reasonable , This hinders its adoption . Higher quality and formalized RISC-V IP Will help it bridge the gap , And increase its adoption rate on a large scale .”

Codasip Validation director Philippe Luc Add :“ We are very proud of our strict verification methods and strong internal verification team . We have extremely thorough internal testing methods , Combined with first-class third-party tools . As part of it , We are happy to use Siemens EDA Of OneSpin technology , This is a Codasip Key partners of , We look forward to closer and fruitful cooperation .”

Codasip Use Siemens EDA( Formerly known as Mentor Graphics) As its main EDA Tool flow .

Codasip On 5 month 4 Day in Santa Clara Held Siemens EDAUser2User2022 Its use was introduced at the meeting OneSpin Experience with tools , And will be in 5 month 12 Held in Munich on the th Siemens EDA User2User2022 At the meeting, its experience was introduced again .

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